1. Field of the Invention
This invention relates to a two-dimensional coding apparatus for two-dimensionally coding binary image data, and more particularly to a coding apparatus wherein binary image data are read in from a FIFO (first in first out) memory.
2. Description of the Related Art
Various two-dimensional coding apparatus are already known, and an exemplary one of conventional two-dimensional coding apparatus is shown in FIG. 4. Referring to FIG. 4, the two-dimensional coding apparatus shown includes an image data memory 11 into which binary image data 101 for a plurality of lines are written from the outside. The image data memory 11 further receives, from a two-dimensional coding circuit 5, an address for sequential reference line data or an address for coding line data obtained by a two-dimensional coding procedure as a memory address 207 and simultaneously receives a memory read-out signal 201 from the two-dimensional coding circuit 5. Consequently, binary image data 106 are read out from the image data memory 11 and supplied to the two-dimensional coding circuit 5, in which they are two-dimensionally coded. A resulting code 105 is outputted from the two-dimensional coding circuit 5.
In the conventional two-dimensional coding apparatus, each time coding of binary image data for a number of lines which can be stored at a time in the image data memory 11 is completed, new binary image data must be written into the image data memory 11. Consequently, the time necessary for the write processing increases the coding time of the two-dimensional coding apparatus remarkably when a large number of data are to be coded.
Another exemplary one of conventional two-dimensional coding apparatus is shown in FIG. 5 which employs, in place of the image data memory, a FIFO memory by which binary image data inputted from the outside can be processed sequentially. Referring to FIG. 5, the two-dimensional coding apparatus shown includes two FIFO memories including a reference line FIFO memory 1 and a coding line FIFO memory 2. First, binary image data 101 for one line are written at a time into the reference line FIFO memory 1 and the coding line FIFO memory 2 from the outside.
Meanwhile, an upper address for reference line data is written into an address latch 7 from an external host computer by way of a host bus 209 before coding is started. After coding is started by a coding circuit 5, the coding circuit 5 outputs a memory read-out signal 201 and simultaneously outputs an address for coded line data obtained in accordance with a two-dimensional coding procedure or for coded line data conforming to an interrupt request for reference line data or an address of reference line data as a memory address 207.
In the processing, the value 206 set to the address latch 7 is compared with an upper address of the memory address 207 outputted from the coding circuit 5 by a comparator 6, and when coincidence is determined, the comparator 6 puts into an active state a signal 208 representing that data to be currently read into the coding circuit 5 are reference line data.
When both of the memory read-out signal 201 and the signal 208 from the comparator 6 are active, a readout signal 205 for the reference line FIFO memory 1, which is outputted from a first AND gate 9, is put into an active state, but when both of the memory read-out signal 201 and an output signal 209 of an invertor 8, which inverts the signal 208, are active, another readout signal 204 for the coding line FIFO memory 2, which is outputted from a second AND gate 10, is put into an active state.
When the signal 204 is active, binary image data 102 read out from the coding line FIFO memory 2 are read into the two-dimensional coding circuit 5 by way of a multiplexer 3, but when the signal 205 is active, binary image data 103 read out from the reference line FIFO memory 1 are read into the two-dimensional coding circuit 5 by way of the multiplexer 3, and two-dimensional coding is effected by the two-dimensional coding circuit 5. Thus, a resulting code 105 is outputted from the two-dimensional coding circuit 5.
With the two-dimensional coding apparatus shown in FIG. 5, however, each time two-dimensional coding of data for one line is performed, an address for reference line data must be set to the address latch 7 as seen from FIG. 6, and coding processing cannot be performed during the setting operation. Accordingly, much time is required to effect coding for a plurality of lines.